Today's electronics systems contain many complex integrated circuits operating at very high clock frequencies. Already today the data rates on the chip-to-chip interconnects operate at more than 300 Mb/s. It is expected that these data rates will approach 1 Gb/s in the next few years. At these data rates, chip-to-chip interconnects behave like RF transmission lines. As such, proper termination is a must. For longer distance interconnects, parallel termination is often used. Some well known examples include CPU to North Bridge chip interconnect, North Bridge to DDR (Double Data Rate SDRAM) memory interconnect and Graphic processor to DDR memory.
As the width of interconnects gets wider, the amount of power needed to operate these transmission lines may become one of the largest power users of the systems. For example, an advanced graphic processor today may use a 256 bit wide interconnect to the DDR memory. The amount of current flowing through the termination resistors is so staggering that DC/DC converters are often used to provide the termination voltage.
Conventional DC/DC converters typically do not provide fast enough response to the changing demand of the termination current. Even for interfaces running at 300 Mb/s data rates, the current loading may transition from almost zero to full power and back to zero in a matter of a few clock cycles when all of the data bits switch from zeroes to ones and back to zeroes. The problem that faces the DC/DC power supply for the termination voltage is also encountered at the DC/DC power supply for the driver circuits that drive the transmission line.
FIG. 1 shows a conventional driver power system 10 that includes a driver power supply, VDDQ, 12 and capacitor 13 to supply energy to high speed line drivers 14 (one of many shown), and a termination power supply, VTT, 16 and capacitor 15 to supply energy to termination devices 18.
In operation, the drivers 16 draw current from the driver power supply 12 as a function of the state of the data lines 19. Small currents flow when all or most of the data lines are in the low state. When most of the data lines are in the high state, a large DC load current flows. During a high load current mode, the current flows from the VDDQ power supply 12 through the termination resistors 18, and into the termination power supply 16, which sinks the current. The current flowing into the VTT power supply 16 from the VDDQ power supply 12 is negative and about one-half the magnitude of the current flowing out of the VDDQ power supply 12.
When the data lines 19 switch to the low state, the current from the VDDQ power supply 12 to the termination resistors 18 virtually immediately decreases to zero. This causes the voltage output from the VDDQ power supply 12 to spike upwards, causing the VDDQ power supply to transition to an emergency transient recovery mode to protect the power supply output from increasing beyond the voltage regulation limits. Almost simultaneously, the current through the VTT power supply 16 reverses in direction, causing the voltage of the VTT power supply 16 to spike downwards, sending the VTT power supply 16 into an emergency transient recovery mode to prevent the VTT power supply voltage from decreasing below the voltage regulation limits. The emergency VTT emergency transient recovery operation in return may cause a huge transient current to flow back into the VDDQ power supply 12, further exasperating the voltage spike at the output of the VDDQ power supply 12. The magnitude of the power supply fluctuations during the transient load changes may be decreased by employing high speed DC/DC converters for the VTT and VDDQ power supplies 12 and 16. However, the magnitude of the power supply fluctuations may still be significant and high speed DC/DC converters are generally very costly.